[RHEL7,COMMIT] ms/KVM: LAPIC: Fix lapic timer mode transition

Submitted by Konstantin Khorenko on July 25, 2018, 3:47 p.m.

Details

Message ID 201807251547.w6PFl7wr019142@finist_ce7.work
State New
Series "ms/KVM: LAPIC: Fix lapic timer mode transition"
Headers show

Commit Message

Konstantin Khorenko July 25, 2018, 3:47 p.m.
The commit is pushed to "branch-rh7-3.10.0-862.9.1.vz7.63.x-ovz" and will appear at https://src.openvz.org/scm/ovz/vzkernel.git
after rh7-3.10.0-862.9.1.vz7.63.2
------>
commit 632a7924e3051ccb3712a9d331f8b588a58932fd
Author: Wanpeng Li <wanpeng.li@hotmail.com>
Date:   Wed Jul 25 18:47:07 2018 +0300

    ms/KVM: LAPIC: Fix lapic timer mode transition
    
    SDM 10.5.4.1 TSC-Deadline Mode mentioned that "Transitioning between TSC-Deadline
    mode and other timer modes also disarms the timer". So the APIC Timer Initial Count
    Register for one-shot/periodic mode should be reset. This patch do it.
    
    Cc: Paolo Bonzini <pbonzini@redhat.com>
    Cc: Radim Krčmář <rkrcmar@redhat.com>
    Signed-off-by: Wanpeng Li <wanpeng.li@hotmail.com>
    [Removed unnecessary definition of APIC_LVT_TIMER_MASK.]
    Signed-off-by: Radim Krčmář <rkrcmar@redhat.com>
    (cherry picked from commit c69518c86be5000bf4d8eb0e0d279d40779d2a18)
    Signed-off-by: Viktor Prutyanov <viktor.prutyanov@virtuozzo.com>
    
    This patch differs from original because of different order of functions
    in arch/x86/kvm/lapic.c
    
    https://jira.sw.ru/browse/PSBM-86578
    
    Signed-off-by: Viktor Prutyanov <viktor.prutyanov@virtuozzo.com>
    
    =====================
    Patchset description:
    
    Fix guest context switch performance degradation.
    
    https://jira.sw.ru/browse/PSBM-86578
    
    Following patches were adopted from mainline kernel to fix guest Windows
    context switch performance degradation.
    
    VMX preemption timer support was added in kernel-3.10.0-862.3.2.el7. In this
    case, timer incorrectly triggers despite of its disabling and causes extra
    VMexit on every context switch. These patches add correct handling of disabled
    timer.
    
    Radim Krčmář (3):
      KVM: x86: handle 0 write to TSC_DEADLINE MSR
      KVM: x86: really disarm lapic timer when clearing TMICT
      KVM: x86: thoroughly disarm LAPIC timer around TSC deadline switch
    
    Wanpeng Li (3):
      KVM: LAPIC: Fix lapic timer mode transition
      KVM: LAPIC: Introduce limit_periodic_timer_frequency
      KVM: LAPIC: Keep timer running when switching between one-shot and
        periodic mode
---
 arch/x86/kvm/lapic.c | 3 +++
 1 file changed, 3 insertions(+)

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diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index 3058ba9ed4a9..db52738b82a7 100644
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -1355,6 +1355,9 @@  static void apic_update_lvtt(struct kvm_lapic *apic)
 			apic->lapic_timer.timer_mode_mask;
 
 	if (apic->lapic_timer.timer_mode != timer_mode) {
+		if (apic_lvtt_tscdeadline(apic) != (timer_mode ==
+				APIC_LVT_TIMER_TSCDEADLINE))
+			kvm_lapic_set_reg(apic, APIC_TMICT, 0);
 		apic->lapic_timer.timer_mode = timer_mode;
 		hrtimer_cancel(&apic->lapic_timer.timer);
 	}