[RHEL7,COMMIT] ms/KVM: x86: thoroughly disarm LAPIC timer around TSC deadline switch

Submitted by Konstantin Khorenko on July 25, 2018, 3:47 p.m.

Details

Message ID 201807251547.w6PFlADd019402@finist_ce7.work
State New
Series "ms/KVM: x86: thoroughly disarm LAPIC timer around TSC deadline switch"
Headers show

Commit Message

Konstantin Khorenko July 25, 2018, 3:47 p.m.
The commit is pushed to "branch-rh7-3.10.0-862.9.1.vz7.63.x-ovz" and will appear at https://src.openvz.org/scm/ovz/vzkernel.git
after rh7-3.10.0-862.9.1.vz7.63.2
------>
commit 63b69be3719fea1bd62e333f4416b4f48e38bf31
Author: Radim Krčmář <rkrcmar@redhat.com>
Date:   Wed Jul 25 18:47:10 2018 +0300

    ms/KVM: x86: thoroughly disarm LAPIC timer around TSC deadline switch
    
    Our routines look at tscdeadline and period when deciding state of a
    timer.  The timer is disarmed when switching between TSC deadline and
    other modes, so we should set everything to disarmed state.
    
    Signed-off-by: Radim Krčmář <rkrcmar@redhat.com>
    Reviewed-by: Wanpeng Li <wanpeng.li@hotmail.com>
    Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
    (cherry picked from commit 44275932589a84a24849290b0d5c22157016a5e6)
    Signed-off-by: Viktor Prutyanov <viktor.prutyanov@virtuozzo.com>
    
    https://jira.sw.ru/browse/PSBM-86578
    
    Signed-off-by: Viktor Prutyanov <viktor.prutyanov@virtuozzo.com>
    
    =====================
    Patchset description:
    
    Fix guest context switch performance degradation.
    
    https://jira.sw.ru/browse/PSBM-86578
    
    Following patches were adopted from mainline kernel to fix guest Windows
    context switch performance degradation.
    
    VMX preemption timer support was added in kernel-3.10.0-862.3.2.el7. In this
    case, timer incorrectly triggers despite of its disabling and causes extra
    VMexit on every context switch. These patches add correct handling of disabled
    timer.
    
    Radim Krčmář (3):
      KVM: x86: handle 0 write to TSC_DEADLINE MSR
      KVM: x86: really disarm lapic timer when clearing TMICT
      KVM: x86: thoroughly disarm LAPIC timer around TSC deadline switch
    
    Wanpeng Li (3):
      KVM: LAPIC: Fix lapic timer mode transition
      KVM: LAPIC: Introduce limit_periodic_timer_frequency
      KVM: LAPIC: Keep timer running when switching between one-shot and
        periodic mode
---
 arch/x86/kvm/lapic.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

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diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index c03a1658b578..87cdb267b498 100644
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -1378,8 +1378,10 @@  static void apic_update_lvtt(struct kvm_lapic *apic)
 	if (apic->lapic_timer.timer_mode != timer_mode) {
 		if (apic_lvtt_tscdeadline(apic) != (timer_mode ==
 				APIC_LVT_TIMER_TSCDEADLINE)) {
-			kvm_lapic_set_reg(apic, APIC_TMICT, 0);
 			hrtimer_cancel(&apic->lapic_timer.timer);
+			kvm_lapic_set_reg(apic, APIC_TMICT, 0);
+			apic->lapic_timer.period = 0;
+			apic->lapic_timer.tscdeadline = 0;
 		}
 		apic->lapic_timer.timer_mode = timer_mode;
 		limit_periodic_timer_frequency(apic);