[RHEL7,COMMIT] ms/perf/x86/intel: Print LBR support statement after validation

Submitted by Konstantin Khorenko on Aug. 31, 2018, 3:03 p.m.

Details

Message ID 201808311503.w7VF3GcA005806@finist_ce7.work
State New
Series "perf/x86/intel: Print LBR support statement after validation"
Headers show

Commit Message

Konstantin Khorenko Aug. 31, 2018, 3:03 p.m.
The commit is pushed to "branch-rh7-3.10.0-862.11.6.vz7.71.x-ovz" and will appear at https://src.openvz.org/scm/ovz/vzkernel.git
after rh7-3.10.0-862.11.6.vz7.71.7
------>
commit 1d841c217f8a137d5a90727336eda2145386ce83
Author: David Carrillo-Cisneros <davidcc@google.com>
Date:   Fri Aug 31 18:03:16 2018 +0300

    ms/perf/x86/intel: Print LBR support statement after validation
    
    We have a problem of many "16-deep LBR, " messages fludding dmesg in:
    
    kvm_pmu_refresh
      intel_pmu_refresh
        intel_pmu_lbr_fill
          __intel_pmu_lbr_fill
            intel_pmu_lbr_init_*
    
    By moving these message to __init intel_pmu_init we will see them only
    on kernel init in "Performance Events: ..." line.
    
    Conflicts: Hunks in intel_pmu_lbr_init_knl, intel_pmu_lbr_init_hsw
    skipped and changed x86_pmu.lbr_nr to x86_pmu.lbr.nr because of:
    dbeee2df1c6a ("ms/perf/x86/intel: make reusable LBR initialization code")
    
    https://jira.sw.ru/browse/HCI-131
    https://pmc.acronis.com/browse/VSTOR-14178
    
    MS commit commit f09509b9398b ("perf/x86/intel: Print LBR support
    statement after validation")
    
    The following commit:
    
      338b522ca43c ("perf/x86/intel: Protect LBR and extra_regs against KVM lying")
    
    added an additional test to LBR support detection that is performed after
    printing the LBR support statement to dmesg.
    
    Move the LBR support output after the very last test, to make sure we
    print the true status of LBR support.
    
    Signed-off-by: David Carrillo-Cisneros <davidcc@google.com>
    Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
    Reviewed-by: Stephane Eranian <eranian@google.com>
    Reviewed-by: Andi Kleen <ak@linux.intel.com>
    Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
    Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
    Cc: Jiri Olsa <jolsa@redhat.com>
    Cc: Kan Liang <kan.liang@intel.com>
    Cc: Linus Torvalds <torvalds@linux-foundation.org>
    Cc: Peter Zijlstra <peterz@infradead.org>
    Cc: Thomas Gleixner <tglx@linutronix.de>
    Cc: Vince Weaver <vincent.weaver@maine.edu>
    Link: http://lkml.kernel.org/r/1466533874-52003-2-git-send-email-davidcc@google.com
    Signed-off-by: Ingo Molnar <mingo@kernel.org>
    
    Fixes: commit 493e43ea1a80 ("ms/KVM: x86/vPMU: ignore access to LBR-related MSRs")
    Signed-off-by: Pavel Tikhomirov <ptikhomirov@virtuozzo.com>
    Reviewed-by: Jan Dakinevich <jan.dakinevich@virtuozzo.com>
---
 arch/x86/events/intel/core.c | 2 ++
 arch/x86/events/intel/lbr.c  | 5 -----
 2 files changed, 2 insertions(+), 5 deletions(-)

Patch hide | download patch | download mbox

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 92008f3f0021..740689dd8c48 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -4165,6 +4165,8 @@  __init int intel_pmu_init(void)
 			x86_pmu.lbr.nr = 0;
 	}
 
+	if (x86_pmu.lbr.nr)
+		pr_cont("%d-deep LBR, ", x86_pmu.lbr.nr);
 	/*
 	 * Access extra MSR may cause #GP under certain circumstances.
 	 * E.g. KVM doesn't support offcore event
diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c
index b0946060dea0..aa5ed41f695f 100644
--- a/arch/x86/events/intel/lbr.c
+++ b/arch/x86/events/intel/lbr.c
@@ -946,7 +946,6 @@  static void intel_pmu_lbr_init_core(struct x86_pmu_lbr *lbr)
 	 * SW branch filter usage:
 	 * - compensate for lack of HW filter
 	 */
-	pr_cont("4-deep LBR, ");
 }
 
 /* nehalem/westmere */
@@ -967,7 +966,6 @@  static void intel_pmu_lbr_init_nhm(struct x86_pmu_lbr *lbr)
 	 *   That requires LBR_FAR but that means far
 	 *   jmp need to be filtered out
 	 */
-	pr_cont("16-deep LBR, ");
 }
 
 /* sandy bridge */
@@ -987,7 +985,6 @@  static void intel_pmu_lbr_init_snb(struct x86_pmu_lbr *lbr)
 	 *   That requires LBR_FAR but that means far
 	 *   jmp need to be filtered out
 	 */
-	pr_cont("16-deep LBR, ");
 }
 
 /* haswell */
@@ -1019,7 +1016,6 @@  static void intel_pmu_lbr_init_skl(struct x86_pmu_lbr *lbr)
 	 *   That requires LBR_FAR but that means far
 	 *   jmp need to be filtered out
 	 */
-	pr_cont("32-deep LBR, ");
 }
 
 /* atom */
@@ -1034,7 +1030,6 @@  static void intel_pmu_lbr_init_atom(struct x86_pmu_lbr *lbr)
 	 * SW branch filter usage:
 	 * - compensate for lack of HW filter
 	 */
-	pr_cont("8-deep LBR, ");
 }
 
 /* slm */