[4/9] x86: cpu -- Move xsave testing into fpu capability block

Submitted by Cyrill Gorcunov on Aug. 7, 2018, 4:35 p.m.

Details

Message ID 20180807163517.21669-5-gorcunov@gmail.com
State New
Series "x86: cpu -- Rework feature testing"
Headers show

Commit Message

Cyrill Gorcunov Aug. 7, 2018, 4:35 p.m.
xsave sizes should sit in fpu capability block because
instruction and strick mode checkig is a different
thing.

Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
---
 criu/arch/x86/cpu.c | 42 +++++++++++++++++++++---------------------
 1 file changed, 21 insertions(+), 21 deletions(-)

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diff --git a/criu/arch/x86/cpu.c b/criu/arch/x86/cpu.c
index 5e41a4f86d26..10529260df05 100644
--- a/criu/arch/x86/cpu.c
+++ b/criu/arch/x86/cpu.c
@@ -261,28 +261,28 @@  static int cpu_validate_features(compel_cpuinfo_t *cpu_info)
 		} else
 			return 0;
 #undef __mismatch_fpu_bit
-	}
 
-	/*
-	 * Make sure the xsave features are compatible. We already hit the
-	 * issue with libc where we've checkpointed the container on old
-	 * machine but restored on more modern one and libc fetched new
-	 * xsave frame size directly by xsave instruction with greedy
-	 * feature mask causing programs to misbehave.
-	 */
-	if (cpu_info->xfeatures_mask != rt_cpu_info.xfeatures_mask) {
-		uint64_t m = cpu_info->xfeatures_mask & ~rt_cpu_info.xfeatures_mask;
-		pr_err("CPU xfeatures has unsupported bits (%#llx)\n",
-		       (unsigned long long)m);
-		return -1;
-	} else if (cpu_info->xsave_size != rt_cpu_info.xsave_size) {
-		pr_err("CPU xsave size mismatch (%u/%u)\n",
-		       cpu_info->xsave_size, rt_cpu_info.xsave_size);
-		return -1;
-	} else if (cpu_info->xsave_size_max != rt_cpu_info.xsave_size_max) {
-		pr_err("CPU xsave max size mismatch (%u/%u)\n",
-		       cpu_info->xsave_size_max, rt_cpu_info.xsave_size_max);
-		return -1;
+		/*
+		 * Make sure the xsave features are compatible. We already hit the
+		 * issue with libc where we've checkpointed the container on old
+		 * machine but restored on more modern one and libc fetched new
+		 * xsave frame size directly by xsave instruction with greedy
+		 * feature mask causing programs to misbehave.
+		 */
+		if (cpu_info->xfeatures_mask > rt_cpu_info.xfeatures_mask) {
+			uint64_t m = cpu_info->xfeatures_mask & ~rt_cpu_info.xfeatures_mask;
+			pr_err("CPU xfeatures has unsupported bits (%#llx)\n",
+			       (unsigned long long)m);
+			return -1;
+		} else if (cpu_info->xsave_size != rt_cpu_info.xsave_size) {
+			pr_err("CPU xsave size mismatch (%u/%u)\n",
+			       cpu_info->xsave_size, rt_cpu_info.xsave_size);
+			return -1;
+		} else if (cpu_info->xsave_size_max != rt_cpu_info.xsave_size_max) {
+			pr_err("CPU xsave max size mismatch (%u/%u)\n",
+			       cpu_info->xsave_size_max, rt_cpu_info.xsave_size_max);
+			return -1;
+		}
 	}
 
 	/*

Comments

Dmitry Safonov Aug. 20, 2018, 12:27 p.m.
2018-08-07 17:35 GMT+01:00 Cyrill Gorcunov <gorcunov@gmail.com>:
> xsave sizes should sit in fpu capability block because
> instruction and strick mode checkig is a different
> thing.
>
> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>

Reviewed-by: Dmitry Safonov <0x7f454c46@gmaill.com>

Thanks,
             Dmitry